Memory and 3D Architectures

We wanted to highlight the GSA Memory Conference in San Jose, CA. on March 31. The program title is 3D Architecture with Logic and Memory Integrated Systems. 

GSA (Global Semiconductor Alliance) recently announced a new 3D IC Initiative to help accelerate an industry-wide transition to make 3D IC technically feasible as well as cost effective. We had written of the potential that TSV and 3D IC packaging offers to memory technologies on EDN’s Professor Memory site over a year ago in January 2010. 

We continue to believe that this packaging concept provides the opportunity for memory companies to establish a higher value in this subsystem configuration of multi-die packages than was possible during the mainframe computing and desktop PC eras. With the emphasis of that original blog on new and emerging memory technologies, we noted that:

“TSV and other 3D packaging technologies provide the manufacturing platform that supports a more controlled and gradual introduction of the new and emerging memory technologies… Rather than a single application such as the PC that propels a single memory technology into ‘winner-take-all’ dominance as was the case with DRAM, I anticipate that the conjunction of 3D packaging, single-core processors, and emerging memory technologies will be the platform that drives a wide range of non-volatile memory technologies into a number of applications.“

This flexibility and potential for more product differentiation is a welcome change to memory suppliers. Samsung and Micron have grasped the implications of this shift and are aggressively pursuing the opportunity. Samsung announced in December that the company “…has begun mass production of 8GB DDR3 memory modules based on the SODIMM form factor used by many notebooks and mobile workstations.” The modules are based on 4gbit, 1.5V, 40nm, DDR3 memory chips using 3D TSV chip-stacking technology operating at 1,333MHz. A single 8GB DDR3 module using the new technology is claimed to offer a 53% power savings compared to two 4GB DDR3 modules. This first product is only a two-chip stack, but the company has previously released very impressive preliminary results using much higher stacking levels.

Micron’s COO Mark Durcan is also reported to have commented at a recent IEEE ISS meeting that Micron is also “sampling products based on TSVs” and that full production of TSV-based 3D chips is slated over the next year to year-and-a-half.

Hynix also announced earlier this month that the company has joined Sematech’s 3D Interconnect program. As a wide range of I/O memory-based products are beginning to gain momentum, the company anticipates that a stacked wide I/O DRAM will be very successful in mobile applications.

The two remaining major memory suppliers, Elpida and Toshiba, have also announced programs since our original blog. Elpida and UMC have had a joint development program for 3D IC Integration development in place since June 2010, and Toshiba announced a plan earlier this month to expand to new types of 3D memory stacks. Toshiba plans to start construction of a new plant in July of this year for a 20nm class NAND along with potential to stack both vertically as well as horizontally.

While some major companies are still searching for an application that justifies the effort, we believe that memory companies have grasped the game-changing potential. As we concluded in the original blog, “The conceptual shift is that the memory technology becomes enabled by the (multi-die) platform, not by a single high-volume application.” The prospects of OEM support for a higher level of product differentiation among memory suppliers may seem a new concept to many, but that illusive goal may be within reach as higher-performance mobile products and single-core processors push toward a wider range of memory performance attributes.

www.convergentsemiconductors.com - Global Analysis of Memory Strategies and Issues

The Next Battle

A little over a year ago, Convergent Semiconductors (writing for EDN’s Professor Memory Blog) commented on the growth components and technologies that targeted smartphones and tablet-like devices rather than mainstream PCs.

Convergent Semiconductors’ Observation of where we are today has not changed.  Advanced die-stack solutions are in the mobile devices that dominate semiconductor expanded demand.  System design is defining the low power-using, non-volatile memory as well as new processor solutions for the market-driving mobile consumer devices such as Smartphones, eBooks, and tablets.  Other mobile products such as the notebook, netbook, digital camera/camcorder and other mobile devices continue to grow as part of the mobile segment.

Sales for the top-three mobile products exploded in 2010 over 2009 with an increase of 70%: Smartphone sales grew by 65%; eBook by over 350% and the tablet went from 0 to 18 million units.  Remember that 2010 was not the most robust economic situation and the unit numbers are even more impressive.

Convergent Semiconductors shows that the new mobile products (Smartphones, eBooks and Tablets) were about one-fifth of the mobile product market in terms of units in 2010.  By 2012 those products are expected to be a third and by 2015, half of the mobile products.  This includes continued growth in established mobile products such as the notebook, standard cell phone, portable gaming and some yet unidentified new consumer products.

New Mobile Products Changing the Target Applications

 

 
Here is the previous article:
The New York Times had an interesting article last week that follows the theme of earlier blogs.  The article (For Chip Makers, the Next Battle is in Smartphones) is here:

According to the author, the “chip wars” are entering a new phase as manufacturers fight to supply the silicon for one of the fastest-growing segments of computing: smart phones, tiny laptops and tablet-style devices.  The author concludes that the new conflict is “about to become even more bloody” as the manufacturers and supporters of processor architectures choose sides.  The turf being fought over is the architecture of mobile devices, and the argument that this is different from the previous processor battles is based on the observation that new components and technologies are targeting “smartphones and tablet‑like devices rather than mainstream computers.”

Will the memory manufacturers remain in a neutral support role as they were during the desktop PC era?  I think not. This shift in the target application changes the value proposition of the associated memory technologies.

From the point of view of the memory world, the New York Times article doesn’t describe a “chip war” among processor manufacturers as much as a “platform war.”  In this interpretation of the conflict, the forward edges of the battle lines are shaped by whether this highly anticipated mobile market segment favors a laptop computing platform or a cell phone communications platform.  In the previous processor battles over desktop PCs, architectural participation by memory companies was largely restricted to competing on manufacturing costs based on a single widely supported standard memory interface.  The difference this time is that the memory companies become much more influential in the definition of the performance of target mobile applications than in the desktop PC era.  The memory characteristics of access time, nonvolatile data storage, and total power consumption begin to determine a bigger percentage of the total system value.
 
For example, the list of potential market entry points identified in the previous blog highlighted the possibility of nonvolatile STT-MRAM providing a “universal memory” solution.  This memory architecture may have difficulty in gaining near-term acceptance in desktop PCs, but it could be ideal for laptops and tablet-style devices by reducing the power consumption, improving the overall performance, and providing instant-on capability.

Additionally, die-stacked technologies that are already commonly used by memory companies can also provide unique capabilities for high-end cell-phone platforms.  Advanced die-stacked technologies can offer the wider selection of mix-and-match configurations necessary to support a cell phone end-user mentality that demands a much wider set of performance and cost options along with a much faster time-to-market for new features.

Let’s also not forget the company that is the largest memory manufacturer and the world’s second-largest semiconductor company also has a big stake in this platform battle.  That company, Samsung, is also the second-largest supplier of cell phones and has already partnered with one of the primary processor suppliers.

According to the New York Times article, Jim Ballingall, vice president for marketing at GlobalFoundries, commented that, “This is a game changer.”  I suspect memory companies—both old and new—will very strongly agree with that opinion.”

www.convergentsemiconductors.com - Global Analysis of Memory Strategies and Issues

SSD Trends lead toward New Memory Technologies

Solid State Disk (SSD) demand is pushing in two directions; SSD and USB flash drives for mobile consumer applications, as well as higher-performance SSDs for server-level performance improvements in data retrieval. Both market trends are well established and easily differentiated.

There are, however, several technical barriers ahead for NAND endurance related to block erase/write cycles as cell sizes shrink and as page sizes increase. The endurance of the cells is reduced in both cases, but the application impact and response is not the same for both the consumer and enterprise applications.

Mobile consumer applications are cost/density driven and the potential solutions are more easily addressed due to the shorter product life expectancy.

The duty cycle life expectancy of the higher performance enterprise applications is more challenging. Providing hot-swap capabilities for NAND boards as they approach the end of their reliability limits is a well-proven method to assure the reliability of the data, and the additional cost of substituting new boards as older boards approach the end of their useful life is easily justified relative to the increase in performance.

However we are likely to eventually experience a fundamental shift in the historic progression of the memory cost/performance equation as smaller geometry manufacturing processes of today's technologies inevitably begin to reduce the endurance characteristics of erase/re-write cycles.

Deviations from the traditional decline in the cost-per-bit due to increasing manufacturing challenges at sub-20nm processes, as well as any additional architectural and error-correction requirements necessary to assure the reliability of the data, will slow the rate of decline in the bit cost of the memory technology and provide market entry points for newer semiconductor memory technologies.

This is an important element in the product development path that leads to the introduction of new memory technologies with their plethora of new high-performance attributes. The assumption that existing memory technologies-particularly NAND-can continue the traditional annual decline in the cost-per-bit indefinitely without a reduction in the performance characteristics is no longer considered valid.

www.convergentsemiconductors.com - Global Analysis of Memory Strategies and Issues