Crocus Advances its MRAM Business and Manufacturing Infrastructure

Crocus continues commercializing its Magnetic Logic Unit (MLU) MRAM at an impressive rate.  MLU MRAM is a variety of the general category of thermally assisted (TAS) MRAM.

On the IP side of the equation, Crocus extended its technology base to over 100 issued and pending patents in magnetic semiconductor technology after the recently announced acquisition of the MRAM patent portfolio of NXP Semiconductors in Eindhoven, Holland. The company’s wide range of IP now covers materials and devices, as well as design and product technology.  Additionally, Crocus and IBM recently announced a joint agreement that includes technology co-development and cross licensing to merge their MRAM technologies, including access to IBM’s processing capabilities.

Crocus has also achieved a formidable manufacturing base.  Following an initial R/D partnership with SVTC in San Jose, California and existing production at its foundry partner Tower Jazz Semiconductor, the new IBM agreement also allows Crocus access to technology beyond the current 130-nm mode supported by Tower Jazz.  The IBM agreement might also provide technological assistance to the Crocus venture with the Rusnano-funded subsidiary Crocus Nano Electronics (CNE) for the eventual production of high-capacity stand-alone MRAM wafers.  The CNE fab is expected to be in operation in 2013 at 90- to 65nm, with the potential for finer process technologies in the future, and will have the capability to add MRAM-specific processing layers to standard 300-mm CMOS wafers.

Crocus has also recently established a source for those base wafers—China’s Semiconductor Manufacturing International Corporation (SMIC).  The two companies announced on December 9 a joint technology and wafer manufacturing agreement under which a high-temperature MLU MRAM technology will be developed.  SMIC will manufacture the CMOS base wafers; final processing is planned to take place at CNE.

The advances in the product marketing should also not be overlooked.  Crocus recently announced a joint program with French startup Starchip to develop MLU memory and logic functionality for next generation secure processor-based architectures.  Starchip’s three cofounders, formerly members of Atmel’s Smart Card Business Unit, recently raised 1.5 million € during the company’s third round of financing.

This program in turn supports a previously announced agreement between Crocus and Morpho, a leading supplier of e-document solutions in Europe, to develop Smart Cards based on MLU technology.  Crocus’ MLU technology is expected to replace the NAND Flash technologies used in the first generation of the Smart Cards.

Any new and emerging memory technology has to eventually deliver the anticipated value, and there is no reason to doubt that Crocus’ MLC will succeed.

In the meantime, Crocus is developing an extremely focused and well-coordinated business and manufacturing infrastructure.

www.convergentsemiconductors.com - Global Analysis of Memory Strategies and Issues 

IMEC Paper at IEDM Presents 10x10nm ReRAM Memory Cell

In our previous blog regarding Micron and Sony’s ReRAM program, we had also identified IMEC’s program in exploring some of the potential features of the technology. Today it is reported that one of the 17 papers being presented this week by IMEC at the 2011 IEEE Electron Devices Meeting includes a fully-functioned HfO2-based ReRAM cell with an area of less than 10x10nm.

The press release also points to the general concern within the industry that the increased complexity in continuing to scale today’s high-volume memory technologies is one of the motivations for the research in new memory cell technologies.

In our blog of May 2 titled "Is the Semiconductor ‘Memory Wall’ Finally Crumbling?", we observed that barriers also loom ahead for logic designs for a different set of reasons. The manufacturing challenges of 3D transistors and the ability to cost-effectively achieve the performance potential of multi-core processors are all likely to be no less challenging that those related to new and emerging memory technologies.

To increase the sense of urgency even while these two major semiconductor industry elements of memory and logic are preparing to meet those manufacturing challenges, the fundamental target applications for the development of new memory technologies is rapidly shifting from the single focus of the desktop PC era toward a much more diversified set of OEM expectations. The completed picture includes not only the diverse and still-evolving expectations of server and data storage applications we previously discussed, but the equally challenging trend toward providing mobile solutions for any data collection or personal computing application.

This rapidly-evolving market environment obsoletes a widely-held view of the past 20 years’ history of memory technologies that any new memory product has to compete with an existing high-volume product on a cost-per-bit basis before it will ever be accepted. Regardless of the technology, the true equation has always been that the competition is based on both cost and performance, but the single-application focus on desktop PCs for the past decade effectively masked any support for a wider set of memory performance attributes.

While IMEC’s paper does not necessarily validate one memory technology over all other contenders, the concluding sentence of the press release certainly demonstrates the breadth of interest in new and emerging memory technologies: “These results were obtained in cooperation with IMEC’s key partners in its core CMOS programs Globalfoundries, INTEL, Micron, Panasonic, Samsung, TSMC, Elpida, Hynix, Fujitsu and Sony.”

Contact us (bobm@convergentsemiconductors.com) for information for Convergent Semiconductors’ hot-topic report on ReRAM regarding applications, challenges and infrastructure opportunities.

www.convergentsemiconductors.com - Global Analysis of Memory Strategies and Issues 

Micron and Sony Resistive RAM Joint Development Program

There was a recent—and extremely brief—reference to a joint development program between Sony and Micron on ReRAM that was reported from comments made at a recent media roundtable. This article on November 28 attracts more speculation due to the lack of details rather than the information contained in the press release.

"(Jiji Press English News Service Via Acquire Media NewsEdge) Tokyo, Nov. 28 (Jiji Press)--Sony Corp. said Monday it has started to develop a next-generation memory chip with Micron Technology Inc. of the United States.

Sony aims to make the resistance random access memory, or ReRAM, commercially available over the next three or four years.

The chip has the potential to become a major business, Sony Executive Deputy President Hiroshi Yoshioka said at a press conference."

This joint development also follows a Micron announcement a month ago of a technology collaboration with Singapore’s Data Storage Institute on STT MRAM.

Considering Micron’s previous high visibility acquisition of Intel’s Phase Change Memory (PCM) program, these new announcement are likely part of the regular activity of all memory companies to keep abreast of any potentially critical new technologies.

However, Micron already has a long history in ReRAM that can be traced back to there 2002 licensing of Axon Technologies’ Programmable Metallization Cell (PMC) technology.

Axon’s program is considered by many to be the initial source of the current interest in the growing family of resistive memory cell technologies. You may recall that Infineon was developing a version of the technology under the name of CBRAM that was based on a 2004 license with Axon. As IMEC and other companies continue to explore a wide range of materials that broadly fall into that category of resistive RAM technologies, the ReRAM with the most momentum at the moment is likely the Adesto development program that had also acquired the Infineon/Qimonda CBRAM IP.

While the public perception of memory technologies tends to assume that no new technology will be acceptable until it reaches the same cost per bit of DRAM or NAND, we believe that the continued interest in these new and emerging technologies is based on finding other market entry points and an expectation of providing high value to new applications.

In the specific case of Micron’s recently announced activities in these two additional technologies, it does raise the question of how that company can best allocate resources among DRAM, NAND, Hybrid Memory Cube, Reduced Latency DRAM, PCM, ReRAM, and STT MRAM. However since Micron remains the oldest existing high-volume memory company and has therefore weathered more market and technology storms than any other memory company, they have certainly gained the experience to combine these technologies into a cohesive package.

Even if this does look like an unworkable mash-up at first glance, we also believe that the performance attributes of PCM, ReRAM, and STT MRAM will all eventually support different applications anyway. As we have stated before, our market model is one in which the value proposition of the memory technologies increases as the industry moves further away from the desktop PC era and into the new era of multiple targets for the development of new memory technologies.

While it is not clear yet how quickly these new memory technologies will reach high volume production, there are two trends that are becoming more pronounced. One trend we have previously reported is that OEMs are asking for a wider range of memory technology performance attributes than any time in the past.

Micron’s recent technology announcements underline the second trend—that memory companies also anticipate changes in the traditional market conditions and are responding with technology development commitments for new and emerging memory technologies.

www.convergentsemiconductors.com - Global Analysis of Memory Strategies and Issues 

JEDEC Memory Conference Emphasizes the Increasing Impact of Servers

Semiconductor Manufacturing and Design reported on the recent Jedec Server Memory Conference in San Jose. That article is titled “Facebook Wants New and Cheaper Memories.” We also attended that conference and our opinion of the presentations, “New applications like Facebook are driving the industry,” was included in that coverage of the conference.

Servers will continue to be one of the most important applications defining future memory products. As we pointed to in the previous blog on a completely different memory configuration, “servers” clearly designates a function and not a specific architecture. We maintain that the wide range of server tasks, as further demonstrated by Facebook’s categories of server configurations shown in the article, provides the greatest opportunity for experimentation with new memory configurations and performance attributes.

As has already been demonstrated by the substitution of NAND for DRAM in other server applications in which the targeted performance attribute was the reduction in power consumption, server designers are not hesitant to break previously-held assumptions of memory cost/performance when responding to the new and shifting requirements for system-level performance attributes.

For more information on Hybrid Memory and Memory in servers, visit www.convergentsemiconductors.com .

www.convergentsemiconductors.com - Global Analysis of Memory Strategies and Issues 

Hybrid Memory Solution for Enterprise Servers

We have often pointed out that servers have become one of the leading areas for the emergence of new memory products and technologies.  However when one speaks of a “server,” is it the simplistic server below?

Or perhaps one of the servers in the following configuration?

The challenge is that when we refer to a “server,” we are clearly addressing a function rather than a hardware configuration.  With this much variation in the specific tasks that can be performance, it is therefore no surprise that servers have become the primary application for architectural variation and advancement.  The broad variety of server applications has been a rich source of new and innovative memory hardware configurations.  Both system designers and end users have shown themselves to be extremely receptive to any new variations in cost and performance tradeoffs.

The replacement of high-reliability DRAM with limited endurance NAND as a method of lowering the power requirements in servers is one of the most remarkable recent innovations as system designers have clearly demonstrated their architectural design flexibility in the face of rapidly increasing data loads.

Computing infrastructure vendors constantly struggle with system-level cost and performance tradeoffs as they balance between the inherent limits in the performance and endurance of NAND, and the requirement to power and cool DRAMs.  Faced with supporting the increase in world-wide data consumption, the necessity to protect data in case of a power interruption continues to increase in  priority  within that constantly evolving equation.

Viking’s newest product release is a prime example of an innovative application of memory echnologies.  The company’s recently announced ArxCis-NV provides uninteruptable high-performance non-volatile memory modules without the usual limited endurance penalty of NAND and without the maintenance associated with wet battery resources.

The 12.6 GBytes per second throughput of these memory modules is provided by 1333MHz DDR3 DRAM that are familiar to system designers.  The 240-pin DIMM is 30mm high in the current configuration with 25.5mm planned for the next design generation, and three density configurations are supported ranging from 2GB 1Rank up to an 8GB 2Rank configuration.

This latest product offering from Viking provides a very high performance option with the equally important feature of complete backup of the semiconductor industry memory in case of power failure.

Protection against potential data loss results from an elegant solution that combines an integrated SSD, Viking’s own “Data-Mover” logic, and an integrated power management system based onViking’s maintenance-free supercapacitor powerpack. DRAM memory is utilized for the all-important read/write performance, and enough power is stored in an on-module capacitor to transfer the data to nonvolatile NAND in case of a power failure.  The powerpack  is kept charged directly from the DIMM connector and is under the management of Viking’s integrated management circuitry that coordinates the data transfer to the SSD in the event of a power failure.   The resulting modules comply with all JEDEC DDR2 mechanical restricutions and easily integrate into any x86 Servers.  Target applications include RAID storage cache backup, OLTP databases, Enterprise cloud computing and virtualiation servers, as well as SAN management and storage consolidation systems.

We view DRAM and NAND as related technologies rather than two separate product lines.  Viking’s latest product offering is consistent with our perspective of the application overlap between DRAM and NAND technologies, and we believe this hybrid configuration to be important for two reasons.

The first reason we believe this product to be important is the increasing likehood of power fluctuations and interuptions driven by the growth of data consumption.  The power requirements to support volatile DRAM  has already resulted in architectural changes that accomodate nonvolatile NAND in order to reduce the overall memory power consumption.  Viking’s latest product product extends that concept by offering the higher performance of DRAM while still providing the nonvolatile data storage of NAND in case of power interuptions.

The second reason we believe this is an important product is because this application provides a clear cost/performance target for next generation memory technologies.  The ultimate technology for these hybrid memory applications is a non-volatile memory technology with DRAM-like performance and endurance, and there are several such technologies on the horizon that can potentially meet these performance requirements.  We therefore believe that Viking’s product will not only verify the market size and value of these high-performance non-volatile applications, but it also introduces Viking to the developers of the new and emerging memory technologies. as a potential future client.

www.convergentsemiconductors.com - Global Analysis of Memory Strategies and Issues 

Memory Technologies in the Post-PC Era

A recent JEDEC newsletter provided information that “mobile technologies are about to replace their PC equivalents as the center of gravity in the IT market,” based on raw semiconductor sales. The author reported that components supporting mobile applications—which include baseband chips, applications processors, and mobile memory—are likely to “become the underpinning for the complete mainstream market over time. Eventually these low-powered technologies will be produced in enough volume to become viable components in a whole range of products which today would probably attract high-powered PC silicon instead.” The author concluded that as the volume of these technologies supporting mobile applications increased, the higher levels of manufacturing efficiencies of these newer technologies would result in these technologies eventually becoming “…the underpinning for the complete mainstream market over time.”

Data from another recent article pointed to the revenue of mobile memory products increasing 26 percent in 2011 to over $16 billion, which also complimented an additional source projecting that server-use DRAM, mobile DRAM, and other memory used in non-PC applications will contribute more than 50% to the total DRAM bit demand in the second half of 2012. Data provided to our clients from our own internal studies had projected an even higher ratio of mobile product acceptance in emerging countries where mobile products are in high demand.

With PCs now less than 50% of the worldwide semiconductor content, we are clearly leaving the PC era. The recent announcement that Hewlett Packard would exit both the PC and tablet computer markets should have erased any remaining doubt.

HP’s acquisition of Compaq Computers was announced in early September 2001—almost exactly 10 years ago. The companies issued a joint statement at that time claiming the acquisition was a “decisive move” that would provide “significant cost structure improvements.” The announcement noted that the combined company would have annual sales of $87.4 billion—roughly equivalent to the IBM of that period.

This more recent reminder of the transition out of the PC era is not news to corporate technology strategists of memory companies who, if anything, have been ahead of the curve of this market transition.

As we have previously noted, the past decade of very broad research of nonvolatile memory technological alternatives supporting mobile and lower power alternatives appears to be shifting from the pure research phase and into the process development phase. The entire movement toward lowering the power consumption in high-performance server applications by substituting nonvolatile memory technologies and NAND SSD architectures has propelled those technologies into potentially high volume applications, and the field of non-volatile memory technologies being considered for mobile applications continues to expand.

Other advances in the usage of memory technologies outside of main memory for desktop PCs extends to SSD’s as well as new end-product concepts based on leading edge, multi-die packaging concepts.

We have published several reports describing the design flexibility and technology progression path of several high-volume applications that will benefit from development trends in multi-die packaging configurations. Memory companies are very familiar with these trends from their earlier—and much simpler—versions of “multi-die” configurations from the historic evolution of high-volume memory modules. It is therefore not surprising to find memory companies on the leading edge of extending that concept to stacking bare die. Samsung and other memory companies continue to develop innovative packaging concepts. Samsung’s recently announced low-energy 30nm DDR3 memory module using a 3D through-silicon via (TSV) technology RDIMM represents advanced capabilities for a new generation of high-speed, high-capacity servers.

Micron’s eMLC NAND, a much higher endurance version of NAND, is another of the increasing options available for lower power applications.

OEMs are also supporting a wider range of interfaces than in the previous PC dominated era, particularly low power configurations. Another configuration that continues to find growing support is low-latency DRAM, as seen by Micron’s recently announced next-generation product as well as by GSI’s entry into that market.

These events are consistent with the theme we have maintained that the target application for new technologies has shifted away from PCs, toward a wider set of applications. It is easy to recognize that none of the new and emerging memory technologies has targeted the primary memory for PCs as their market entry application. It still needs to be pointed out, however, that the broader set of performance attributes being accepted completely invalidates the typical (and erroneous) retort that ‘no new memory can achieve high volume production until it can compete with the cost-per-bit of PC-oriented DRAM.’

Of all the technologies generally associated in the past with PC-era ICs, it remains our contention that the memory companies are the best-positioned and therefore the most likely to benefit from this transition to a broader set of target applications.

www.convergentsemiconductors.com - Global Analysis of Memory Strategies and Issues 

Grandis and Samsung STT-RAM Agreement

Announcements earlier this week that Samsung had acquired Grandis certainly brought additional attention to Grandis’ spin transfer torque MRAM technology, marketed as "STT-RAM" by Grandis. While early reports indicated that Grandis would be merged into Samsung’s R&D operation, details of the agreement are still unclear since a later press release quoted a Samsung spokesperson that declined to comment on the cost of the acquisition or the size of the stake. However the ability of Grandis’ work in a variation of spin transfer torque MRAM to attract a large suitor is without question.

Samsung has maintained research in several of the new and emerging memory technologies. Their most publicized efforts were with the introduction of PCM into some cell phone models earlier this year, although that activity has been notable lately more for the silence and lack of any further public announcements.

While the Samsung/Grandis announcement was surprising in the sense that Grandis had established an earlier partnership with Hynix, Samsung was already known to be involved in research efforts in MRAM. Samsung reported progress on the company’s own STT-MRAM research at the most recent IEDM conference in December 2010. Using a ferromagnetic electrode and a different Magnetic Tunnel Junction structure, Samsung believed their research would accelerate the development of sub-30nm scaling and would continue to scale to sub-20nm levels with STT-MRAM.

We believe that Grandis’ announcement is in line with our previous forecasts. In earlier blogs, we spoke of the increasing maturity of new and emerging memory technologies, and the resulting rise in significance of the manufacturing strategy. While earlier efforts to raise funding was based on spread sheet comparisons of the potential performance advantages, competition is shifting toward a stronger emphasis on the manufacturing infrastructure. Technologies such as Ramtron’s FeRAM and Everspin’s MRAM have been in production and have surpassed the challenges of transitioning from R/D into volume production. The recent commitment of RUSNANO to provide manufacturing support Crocus’ TAS-MRAM, Intel’s transfer of their PCM program to Micron, as well as the partnership between Adesto and Altis are additional indications of this shift.

We believe that this recent Samsung/Grandis announcement falls into that same category of accelerating the transition to a new phase of commercializing new and emerging memory technologies.

www.convergentsemiconductors.com - Global Analysis of Memory Strategies and Issues 

Adesto/Altis Announcement Highlights Manufacturing Progress in New and Emerging Memory Technologies

Adesto has announced that it will ship CBRAM products this year manufactured by foundry partner Altis Semiconductor AS. Adesto plans to sample a 1Mbit serial EEPROM replacement in the second half of this year following its two and a half year collaboration with Altis on the development of the technology. Adesto’s CBRAM technology is based on a programmable metallization cell (PMC) technology licensed from Axon Technologies, which commercialized this technology developed at Arizona State University. This program would mark the first commercial introduction of resistive RAM.

Altis Semiconductor, located in Essonne, France, is known to those following new and emerging memory technologies as the previous site of much of the MRAM joint development of IBM and Infineon, as well as Infineon’s own efforts as an Axon licensee in 2006. Originally established under IBM-France and having gained a wide range of experience in memory technologies, the Altis facility today is an independent enterprise already serving several market leaders in industrial, computer, consumer, micro-controller, and networking market segments.

This announcement from Adesto and Altis highlights a gradual shift in the competitive landscape among the developers of new and emerging memory technologies. Since we first became involved in these technologies over eight years ago, the leading edge of competition has clearly extended beyond creating investment interest based on technical papers and spreadsheets. We have now truly entered the arena in which the manufacturability of the technology begins to dominate the discussions.

By way of measuring the increased attention to manufacturing progress of emerging memory technologies over the past year, we can point to the ongoing production of MRAM and particularly Ramtron’s FeRAM strategy with its fab partner IBM. Also noteworthy are Samsung’s PCM gambit into cell phones late in 2010, RUSNANO’s commitment to provide a turnkey TAS-MRAM facility in the Moscow area in conjunction with Crocus, and now the entry of Altis into the production of Adesto’s CBRAM.

This most recent announcement certainly does not close the door to other technologies that also appear to be on the cusp of production, such as Grandis’ STT MRAM. Companies with considerable internal investment potential, such as HP’s Memristor program and additional programs from IBM and Samsung, are also certainly not shut out of the competition.

We also continue to point out the growing number of new interfaces and applications such as Enterprise SSDs as an indicator of the ability of memory technologies to be accepted for a wider set of performance attributes than was the practice for commodity DRAMs during the extention of mainframe architectures down to desktop personal computers.

The corollary of this shift toward OEM acceptance of higher value proposition memory technologies leads us to believe that the competition among suppliers of new and emerging memory technologies will not lead to a single dominant commodity configuration at this phase of Makimoto’s wave.

However, the importance of the manufacturing strategy timeline for any new and emerging memory technology has clearly been elevated over the past year.

www.convergentsemiconductors.com - Global Analysis of Memory Strategies and Issues 

SiP and Emerging Memory Technologies

Elpida Memory Inc., Powertech Technology Inc. (PTI), and United Microelectronics Corporation (NYSE: UMC; TSE: 2303) ("UMC"), recently announced that they have finalized the 3-way tie-up to deliver 3DIC integration technologies for advanced processes including 28 nanometer (nm). UMC and PTI engineers have already been working with Elpida on joint development of TSV products at Elpida's Hiroshima Plant. This collaboration leverages the strengths of Elpida's DRAM, PTI's assembly, and UMC's foundry logic technologies to develop a one-chip 3D IC Logic+DRAM integration solution.

By now it must be obvious to all that a major change in the strategies of the semiconductor memory companies is well under way. We have seen the development of new memory applications such as Enterprise SSDs replacing DRAMs in servers, arrival of new well-funded memory startups such as Adesto, expansion of suppliers into existing applications such as GSI’s recently announced support of Low Latency DRAM, expansion of the number of high-volume standardized memory interfaces such as Low Power and Wide-I/O DRAM, a broader array of large organizations investing in the research of new memory technologies such as IMEC and some state-supported research organizations, as well as the recent arrival of well-funded new investors such as RUSNANO.

What has been missing to the outside observer has been the reason why anyone would want to invest that much effort to supersede commodity products.

Elpida’s announcement completes the grand strategy of which we have been advising our semiconductor and investment clients over the past two years. In a series of reports we began releasing over a year ago, we have described the future impact of TSV and 3D IC logic+memory integration solutions, the phases of development that will accompany this shift, and the significant role that will be played by new and emerging memory technologies. 

System-in-Package (SiP) solutions are now solidly on the ITRS roadmap and are accorded the same potential future significance as Moore’s Law. There are certainly additional SiP manufacturing challenges to be solved, but clearly none that are significantly more challenging than the announced conversion of microprocessor production to 3-D FinFET technologies, or the traditional decline in cost-per-bit of DRAM and NAND as lithographies scale below 20nm.

Makimoto’s Wave, the market forces first observed by the former CTO of Hitachi’s semiconductor operation, describes periodic shifts in the emphasis of technology development from an emphasis on standardization to customization of technology development. In this transition from larger box-level computing devices toward smaller mobile and personalized computing devices, SiP can often offer greater product flexibility and faster time-to-market than other solutions.

Within that structure, the richness of new performance attributes from new and emerging memory technologies contributes to a higher level of the total system-level value.

www.convergentsemiconductors.com - Global Analysis of Memory Strategies and Issues 

Learning Curves, SSOs, and Grand Strategies

Wikipedia defines “learning curve” as “a graphical representation of the changing rate of learning for a given activity or tool.” Learning curve theory is often referenced in the continuing efforts to reduce the average manufacturing cost of individual components, and the semiconductor utilization of the theory leads to an anticipation of decreasing manufacturing costs as a function of the number of units manufactured in a measured increment of time.

This concept is tied to another equally important, but often overlooked, role of Standards Setting Organizations (SSOs) to facilitate an infrastructure of support so that design activities can precede the actual availability of the next-generation product.  This insures that there is an established level of demand waiting as the new device ramps into production.

The combination of these two elements traditionally established a series of applications for new memory products, by which progressively higher volume applications transition to the next generation of memory product as the price per bit declined.  Although the highest volume application to convert was typically the desktop PC, that application tended to delay conversion to the newest and highest density product until the per bit cost was equivalent to the previous DRAM product generation.  This tends to be the common approach to increase the market share for any new product, and the decline in the price per bit of the memory technology is eventually a function of the total number of components manufactured and the fundamental manufacturability of the technology itself.  The concept leads to the careful selection of a market entry point and the identification of a series of applications with increasingly higher volume demand and increasingly lower cost targets. 

The previous blog ($300M Investment in Crocus’ TAS-MRAM) described a major investment by RUSNANO in support of TAS MRAM.  How does this measure up against the traditional approach described above?  Let’s revisit the practical marketing aspects of the learning curve theory.  Although the technical benefits of learning curve theory are well documented for established high-volume products, the theory is less effective as a tool for predicting the success of new technologies—particularly when those new technologies are being used to support new OEM applications. 

The recent TAS MRAM fab commitment by RUSNANO marks a different approach in which a grand strategy is envisioned that includes a substantial up-front investment rather than waiting for the growth in volume that traditionally resulted from the replacement of the previous generation of products with ones of roughly similar performance attributes.  The MRAM technology still has to demonstrate the manufacturing efficiencies and performance attributes to satisfy the needs of OEMs.  The distinction in this case, however, is that the initial growth in manufacturing and R/D knowledge will occur at a faster rate than can be obtained by relying only on learning curve benefits and the application-by-application replacement of an existing high-volume product.

The potential impact we see from the RUSNANO investment in TAS MRAM is that this high level of investment may also encourage enough support among potential OEMs to commit to the new technology at an earlier phase in the product development cycle.  As has been demonstrated by the increased usage of NAND to replace DRAM in some server architectures, the ability to influence the architecture of potential new OEM designs can be based on a broader set of criteria than the existing level of knowledge and specs.

It is this ability to potentially influence or stimulate new architectural designs that has now been introduced.  Data sheet comparisons of performance specs are always meaningful, but let’s not forget that the objective with new technologies is to influence the OEM’s future designs and new applications, and not necessarily to create a superior set of performance attributes for existing applications.  

We believe that the next phase of commercialization of new memory technologies has now begun.  OEMs have a basic understanding of the potential of the technologies as well as a perception of the fundamental shift in target applications for the new and emerging memory technologies, and the forward edge of competition is now shifting toward the manufacturing infrastructure.

www.convergentsemiconductors.com - Global Analysis of Memory Strategies and Issues 

$300M Investment in Crocus’ TAS-MRAM

Crocus has announced an investment of $300 million in the company and its Thermally Assisted Switching™ MRAM.  The investment comes from RUSNANO for creation of a manufacturing facility in Russia for medium- to high-density MRAM.  The two companies will form Crocus Nano Electronics (CNE) to build an advanced MRAM production facility in Russia capable of producing 90nm and 65nm material on Crocus’ TAS-MRAM technology.

Under the terms of the agreement, $125 million will be committed in the first year to set up the fab, and the existing investors of RUSNANO and Crocus will make an equity investment of $55 million into Crocus for additional technical development.  An additional $120 million will be scheduled for subsequent years for additional increases in the production capacity.  Further investments will be made at a later date in order to support future upgrades to 45nm processing.

The manufacturing flow will be designed to add MRAM-specific features within a standard 300mm CMOS process.   Initial operation is expected to begin within 2 years at 500 wafers per week, with the potential to double that capacity in a later phase of investment.  Crocus will also invest over $5 million initially into Russian research organizations in order to develop other advanced manufacturing solutions as part of the support infrastructure.

This manufacturing strategy compliments Crocus’ existing 130nm foundry partnership with TowerJazz, which is currently in the final qualification stages with production planned by the end of this year.  Processing contributions of San Jose’s Silicon Valley Technology Center (SVTC) also should be acknowledged.

Crocus’ investor RUSNANO was established through the reorganization of the corporation formerly known as the Russian Corporation of Nanotechnologies.   Anatoly Chubais is now serving as chairman of the Executive Board. In Autumn 2009, the supervisory council of RUSNANO approved the corporation’s participation in a new Russian venture fund established in partnership with VTB Group and well-known Silicon Valley investment company Draper Fisher Jurvetson to focus on promising nanotechnology innovation.  RUSNANO has since committed $5.9 billion to 110 projects with more than $2.4 billion already invested, and has opened an office on Sand Hill Road in San Jose.

One of the competitive elements we advise clients engaged in new memory technologies to heed in their business development practices is to avoid becoming too focused on the item-by-item comparison of their data sheets with those of their potential competitors.  Participation in emerging markets and with emerging technologies often includes another important element, which is the ability of a competitor to exert an influence on the architecture of future products beyond just the performance attributes of the data sheets.  We place this announcement by Crocus in that category of potentially game-altering events.  The commitment to a significant volume of manufacturing capacity by CNE and the presence of an influential new supporter in RUSNANO has to be acknowledged as substantially raising the ante in the development of new memory technologies.

www.convergentsemiconductors.com - Global Analysis of Memory Strategies and Issues 

Panasonic ReRAM Samples Scheduled for Late 2011

Panasonic issued a brief announcement today that the company anticipates availability of 2 megabit ReRAM samples by the end of this year, with expectations of mass production in 2012. The company intends to focus on small-capacity non-volatile ReRAM configurations intended for home electronic products.

ReRAM tends to cover a wide range of materials, and it is not clear from today’s brief announcement what material was used in the process.

However the announcement follows a paper presented at the International Electron Devices Meeting (IEDM) in San Francisco in December 2008. That paper described a tantalum and oxygen (TaOx) process for a non-volatile memory cell with endurance over 109 cycles and data retention in excess of 10 years at 85 degrees centigrade. At that time, the company had produced 8 Kbit 1T1R memory arrays using a standard 0.18 micron CMOS process.

Key words: ReRAM Panasonic Tantalum TaOx

www.convergentsemiconductors.com - Global Analysis of Memory Strategies and Issues 

FRAM Perspective

2011 has been a hectic year so far for FRAM programs.

After achieving total revenue of $47.5 million for 2009, followed by total revenue of $70.2 million 2010, the first quarter of this year brought organizational changes to Ramtron as well as announcements of delays in IBM’s planned FRAM-foundry program. IBM’s program for a 0.18-micron process began in 2009 with the intention of joining TI and Fujitsu with FRAM foundry services for Ramtron, and production material was intended for 2010.

However the outlook for the technology has improved significantly in May with a major announcement from Texas Instruments. Based on material from the company’s 130-nm technology process, TI has announced the industry's first ultra-low-power FRAM 16-bit microcontrollers with the capability to write more than 100 times faster than Flash and EEPROM-based microcontrollers, while using as little as 250 times less power. Additionally, the on-chip FRAM memory allows data retention in all power modes, supports more than 100 trillion write cycles, and delivers a new dimension of flexibility by allowing developers to partition data and programming memory with changes in software. The FR57xx series eliminates existing power consumption and write endurance barriers, enabling more cost-efficient data logging, remote sensing and wireless update capabilities. The design also enables intelligent battery-less RF connectivity solutions, which have been the hallmark of FRAM’s low power characteristics. Ramtron’s MaxArias series of products also takes advantage of energy harvesting from RF energy. For more information on TI's new FR57xx microcontrollers with proven FRAM memory, follow this link.

TI maintains that its proprietary process technology, jointly developed with FRAM partner Ramtron, enables it to integrate its MCU with an FRAM option along with other analog options onto the same chip. The essence of TI’s new microcontroller lies in its “ultra-low power embedded memory,” according to Scott Roller, vice president of microcontroller products at TI, in an interview with EE Times. “If you can drive down the power consumption, new markets will be created. That’s been always our fundamental belief at TI.” 

TI isn’t the only company to embed FRAM into microcontrollers. Fujitsu introduced a single-chip, 8-bit MCU featuring embedded FRAM in late 2010 which is intended for a variety of general-purpose applications, including consumer electronics products, healthcare and industrial systems. 

We believe that this is once again demonstrates the growing acceptance of product differentiation based on a wider range of memory performance attributes, and we expect that the performance capabilities of MCUs will continue to be an important opportunity for new memory technologies. 

Key words: FRAM, ferro-electric, Texas Instruments, TI, Ramtron, IBM, Fujitsu, MCU, memory technology

www.convergentsemiconductors.com - Global Analysis of Memory Strategies and Issues 

Lithium-ion Battery —Supply Issues Ahead?

Key words: Lithium-ion, battery, li-ion, shortages

The impact of the catastrophic earthquake and subsequent events in Japan are not yet (and may never be) fully understood, EXCEPT that those events have had and will continue to have a real effect on all manufacturers and consumers of lithium-ion power cells. The question for the next few months or so may turn out to be—Got batteries?

The expected 42% annual increase in demand for tablets, eReaders and Smartphones in 2011 has battery vendors looking ahead to substantially increased demand; all other mobile products are forecast to have double-digit demand growth as well. Convergent Semiconductors forecasts that the first impact to lithium-ion battery supply will be felt this May and June.

The Eastern Japan earthquake, tsunami and nuclear power plant news about wafers, semiconductor supply and the impact on automakers has been in the news. What has not been in the news is the effect on the five Japanese chemical companies that supply nearly all materials to the world’s battery manufacturers. Even as the chemical companies recover and repair the direct damage to their plants, the question of the infrastructure problems needs to be resolved. The evacuation zone around the Fukushima Nuclear Power Plant and rolling blackouts are issues that must be taken into account.

All of the top battery companies, Panasonic-Sanyo, Sony, Samsung SDI, and LGC, depend upon chemical suppliers with manufacturing located in the Eastern Japan region. There are seven chemical companies that were damaged by the earthquake/tsunami/power plant disaster. These companies are not all the major suppliers of specific chemicals, but are part of a supply chain that works with an ever-increasing battery demand.

While the Korean battery manufacturers have taken over market share leadership for lithium-ion batteries consumed by PCs and other mobile products, the Japanese material suppliers have remained dominant in the key chemical components for batteries no matter where those batteries are manufactured. May and June will start to exhibit supply interruptions for mobile products ranging from notebooks and tablets to power tools. Expect to see push-outs of new product announcements until a secure battery supply has been established. Meanwhile, tough competitors are using creative cooperation to ensure the user is not forced into some other technology.

For example, Sony committed to produce certain lithium batteries in March and April but could not deliver due to the quake. Panasonic, at Sony’s request, took over production and adjusted the number and types of batteries in order to deliver a workable solution.

Makita purchased lithium-ion batteries for power tools from Sony but now appears to have gone to Samsung SDI for its supply of lithium-ion batteries. According to an insider, Makita placed an exceptionally large battery order in expectation of strong reconstruction demand in the wake of the earthquake.

Lithium-ion batteries are usually available everywhere. They are the ubiquitous item on the bill of materials that OEMs take for granted will always be available…whenever. Then there is a catastrophic earthquake/tsunami/nuclear power plant failure in Japan—home of single source chemicals for the global battery industry. Hence the essential drama of our battery report—which of your high volume, high dollar consumer electronics products depends on a one-dollar li-ion battery formerly manufactured in the Evacuation Zone?

Convergent Semiconductors covers this market to provide a strategic view of the mobile products phenomenon. Expect delays in product introductions and push-outs in delivery because of the broken supply chain of deliveries from chemical companies in Japan to its global customers. The industry will solve this problem. New sources in a variety of locations will be established. The companies in Japan will recover. However, in the near future, batteries will be a limiting component on the BOM. Contact us for more details of report.

www.convergentsemiconductors.com - Global Analysis of Memory Strategies and Issues 

Is the Semiconductor “Memory Wall” Finally Crumbling?

Key words: Memory wall, Furber, ARM, Moore's Law, heterogeneous processing architecture

The observation by Intel co-founder Gordon Moore that the number of transistors on a circuit would double approximately every two years has been one of the most influential concepts in the growth of the semiconductor industry. An almost equally influential observation was the paper by William Wulf and Sally McKee in 1994 titled Hitting the Memory Wall: Implications of the Obvious, which posited that the rate of performance growth of memory technologies was not progressing as fast as was the performance growth of processors. This observation was labeled as the “memory wall,” and became axiomatic of the design concept by which the primary engine for OEM performance was the processor while the memory played a supporting role. In practical terms, this meant to the memory suppliers that the value of the memory products was essentially based on the cost per bit, and the basis for the competition among memory suppliers focused on the manufacturing efficiencies of a single memory product architecture. The primary focus of that competition was the constant reduction in the lithography in order to achieve more memory cells per silicon area.

We have now reached a level of manufacturing efficiency for memory products at which we are beginning to wonder how much further we can push stored charge memory technologies before the mass of the cells is too small to retain enough energy to be reliably used as an efficient information storage device.

Does this issue of continuing reductions in the storage mass of the memory cell represent yet another “memory wall” that further separates the value of memory technologies from the future development of logic devices?

Not necessarily. In fact, perhaps just the opposite effect is taking place.

You may recall Professor Furber, who designed the first ARM processor for Acorn Computers in the mid-80s. The successors to his design are currently enjoying broad success in high-volume mobile applications such as smart phones and tablet computers. Professor Furber recently stated that processors are also beginning to approach a limit at which the physics of the design cannot be supported. According to Professor Furber, the most advanced processors now contain transistors that are 100 to 150 atoms across, and the costs of designing controllable microchips are approaching a financial risk of a magnitude such that it alters the basic tenets of Moore’s Law.

"There are about 10 years to go before we reach the absolute limit. People have been saying that for 30 years, but this time I think it's probably right," he concludes.

Our point is that the technologies of today that are the basis for the high volume production of both logic circuitry and memory products are approaching similar technology hurdles. Regardless of when that hurdle is reached, that challenge will test both logic and memory technologies.

Professor Furber believes that the future architecture for processors will likely be parallel computing with problems split into separate discrete elements and solved simultaneously by different parallel of heterogeneous processing architectures.

We would also suggest that in addition to the shift toward multi-processing elements, the shift toward mobile devices that is already under way is an equally significant change in the market conditions. Shifting the target application for new memory technologies to a wider range of applications that includes mobile and lower power applications broadens the value proposition of the memory technologies beyond the single dominant high-volume commodity product. This new technology development track is distinctly different than memory technologies that extended the memory array architecture essentially from mainframe computers down to desktop PCs as the primary target application for the development of the next generation of high-volume memory technologies. However, this new technology development track for memory technologies is very much in line with the anticipated shift toward heterogeneous processing architectures with individualized memory performance requirements.

We believe that the development of new memory technologies in response to these anticipated hurdles is already far along the path toward commercialization; we may discover that the performance of the memory technologies is not the gating item to the system-level performance as we transition into the next phase of mobile and individualized processing applications.

www.convergentsemiconductors.com - Global Analysis of Memory Strategies and Issues 

Expanding Memory Options with Mobile Product Packaging

Keywords: MCP, SiP, SOC, 3D IC, TSV, Moore’s Law, Multi-Chip Packaging

Why is the activity concerning multi-chip packaging (MCP) technologies increasing?

SEMATECH announced this week that ASE, Altera, Analog Devices, LSI, Qualcomm, and ON Semiconductor have all joined SEMATECH's 3D Enablement program. These companies will join CNSE, GlobalFoundries, Hewlett Packard, Hynix, IBM, Intel, Samsung, and UMC in a broad initiative—and to enable industry infrastructure for TSV-based 3D stacked IC solutions. Also in support of wafer and tool standards for TSV technology, SEMI has three task groups within its 3D IC group, with the formation of a fourth task group under way.

Global Semiconductor Association (GSA) also has a 3D/TSV Technology Working Group. At the recent GSA Memory Conference highlighting 3D Architecture with Logic and Memory Integrated Solutions, one speaker forecasted that stacked multiple wide I/O DRAMs would appear by 2015 using TSV, while another speaker predicted that the TSV-based wide I/O DRAM would not arrive until “…the second half of the decade.” Given the latitude in defining the marketing terms, these two statements aren’t really contradictory. I concluded that we are just a few product development cycles away from the commercial acceptance of TSV stacked memory die products (as early as 2014), to be followed by continuing high-volume expansion of this form factor.

This continuing interest in multi-die packages results from the shift away from Desktop PCs and toward mobile devices as the dominant target applications for new technologies. Product development emphasis continues to shift toward nonvolatile memory and smaller form factors supported by the further empowerment of single-core processors per by Moore’s Law.

Memory technologies immediately enter into the equation for mobile devices anywhere there is are processors. The architectural question is whether the memory requirement is small enough with enough process compatibility to be embedded in in large processor die (up to ~70% of the area in some cases) or System On Chip (SOC), or whether the memory requirement is large, complex enough, or requires enough flexibility in performance attributes to be better suited for a multi-die configuration in TSV or System-in Package (SiP).

That transition opens up the processing R&D and packaging possibilities for memory technologies, as is clearly shown by the ever-expanding number of part numbers and configurations supported by “DRAM companies.”

The broader implication is that the range of memory performance attributes continues to increase as the semiconductor industry identifies a widening set of new applications as targets for the development of new memory performance attributes. This trend implies a wider selection of memory interfaces, packaging options, performance attributes, and densities will continue to be developed. In particular, this leads toward a wider set of performance attributes that include not only the usual speed, density, power consumption, and cost/bit tradeoffs, but we also expect to see other variable performance tradeoffs to extend to cell endurance, latency, non-volatility, compatibility with logic processes, and time-to-market for new configurations.

We follow this trend closely and have several reports listed on our website detailing the strength and pervasiveness of this trend, and market opportunities it presents.

www.convergentsemiconductors.com - Global Analysis of Memory Strategies and Issues 

Samsung/Seagate Announcement Highlights Stress Cracks in Computer Memory Hierarchy

Samsung and Seagate announced a broad strategic alignment today under which Samsung has transferred its hard disk drive operations to Seagate for an estimated $1.375 billion. Included in the agreement, in addition to extensive cross-licensing of existing patents, is a supply agreement under which Samsung will provide semiconductor memory for Seagate’s NAND Enterprise SSD, solid state hybrid drives, and other products.

This alignment reflects a general theme that we—along with Samsung and other observers of memory technologies—have supported for some time.

The general cost and performance guidelines under which memory technologies have developed in the past are now shifting. OEMs and the semiconductor industry are very familiar with the computing memory hierarchy in which the price and performance expectations for memory technologies have been based on the architectural proximity of the memory technology to the processing element. The driving element of this equation was the ability to keep the processing element as busy as possible, and the primary elements of cost/bit versus memory access time defined the values of the associated memory technologies. In terms of performance and cost-per-bit, the traditional top-to-bottom memory hierarchy cost/performance ratio ranked from SRAM, DRAM, non-volatile semiconductor memory, to hard disk drive.

There are two elements that have shifted relative to the original hierarchy. One element is the shift toward mobile computing applications, which naturally elevates the value of non-volatile memory technologies.

The second shift is the massive increase in the amount of data that is being created, transported, and stored, as Samsung and others have pointed out at numerous conferences. The resulting pressure on the computing infrastructure exerted by this increasing data load is causing multiple stress cracks in the traditional computing memory hierarchy. The requirements for lower power consumption and lower heat generation lead to the first major crack, which was the substitution of NAND for DRAM in server applications. That crack has now broadened with the Samsung/Seagate joint participation in Enterprise SSD semiconductor memory products.

We expect that future stress cracks at this and other levels in the traditional computing memory hierarchy will continue to create market entry points for other new memory solutions.

www.convergentsemiconductors.com - Global Analysis of Memory Strategies and Issues 

Fast Clock versus Wide I/O Memory Interfaces

Presentations at the recent Global Semiconductor Alliance Memory Conference also highlighted another traditional memory-related discussion of the data transfer rate of faster clock architectures versus that of wider I/O architectures. During the morning break in presentations, we were asked which would be the highest performance interface architecture for new and emerging memory technologies.

The total data transfer rate performance is of course determined by two elements. The clock rate itself is one element in the calculation; the second element is the number of bits that are transferred at each clock “tick” of the device’s clock The typical shorthand method of only referring to the clock speed of an interface can sometimes be very misleading, and is only a useful measure of performance when comparing two similar architectures.

Both approaches can provide unique system-level values, and the final selection depends on the cost-performance requirements of each application. Wide I/O memory architectures with slower clock rates are usually selected for applications that require a larger number of memory components. In these configurations, system-level designers can achieve additional value from the reduced level of complexity that results from a slower clock rate.

On the other hand, smaller memory arrays that require a very fast data transfer rate can benefit from a different configuration. As explained in the literature for interfaces that utilize faster clock rates and narrower bus interfaces, the cost/performance value of these configurations increases as the number of memory components is reduced. Wide I/O architecture may actually carry an additional cost disadvantage in small memory array applications if the total number of components has to be increased simply in order to accommodate the wider bus width.

It is also useful to consider the end application itself. As long as the memory element of the OEM design continues to hold a secondary level of consideration relative to the processing element (as was common when the processor and operating system defined most of the performance in desktop PCs), other considerations have also been important in the past among OEMs. These other considerations have included such concerns as insuring the broadest base of suppliers, the availability of a wider range of supporting features from third-party suppliers in order to provide more OEM product differentiation, the re-use of existing OEM IP, and the ease of transition to the next generation product.

Specialty applications also have a different set of criteria than those of commodity-like applications. Potentially high-volume specialty memory applications emerging today in which the cost/performance of the memory significantly increases the value of the end product can be seen in the increased opportunities for non-volatile NAND Enterprise SSDs to replace DRAMs when power consumption becomes one of the overriding considerations.

This different set of criteria for new applications has profound significance when considering the most competitive interface architecture for new and emerging memory cell architectures. The market entry point for any new technology begins as a relatively small volume opportunity, yet could represent the opportunity to introduce a new and unique interface.

However, in a case where the cost/performance attributes are comparable between the two architectural concepts, the rate at which the number of memory bits per die is increasing also has be compared to the rate at which the total amount of memory bits in the system-level memory array is increasing. In other words, the system designer has to decide if the total number of memory components is likely to increase or decrease over time in the particular system-level design.

The rate at which a new memory technology progresses in density is particularly difficult to predict. That challenge is made more difficult by the fact that the initial entry point for any new memory technology may not be the highest volume opportunity once the technology becomes more established.

We believe that the most beneficial approach for new memory technologies is to keep all interface options open until the full potential of manufacturability and market acceptance has been demonstrated. New nonvolatile memory technologies that are replacing existing DRAM or NAND in existing applications may find easier market entry by following the protocol and pin assignments of one of the high-volume interfaces as closely as is practical.

Other opportunities to enable a completely new OEM configuration would provide more flexibility in creating a new and more efficient interface. It is in this case of enabling a new set of performance features that the memory architect has to once again consider the specific target applications in choosing between an interface with a fast clock and a narrow data path or an interface with a slower clock combined with a wider I/O interface.

www.convergentsemiconductors.com - Global Analysis of Memory Strategies and Issues 

A Lotta Yotta

At GSA’s Memory Conference on "3D Architecture with Logic and Memory Integrated Solutions" in San Jose last week, Samsung’s "Keynote Address: Rewriting the IT Power Equation" opened with a question to the audience to anyone who could identify the highest industry-recognized scientific notation. The correct answer is the “yotta,” which is 10^24.

Is a number of that magnitude one with which we should become familiar? Absolutely! The notation immediately below the yotta is the zetta (10^21). A zettabyte of information, or a billion terabytes if you prefer, is slightly less than the 1.2 zettabytes of new data estimated to have been created in 2010. By 2020, the amount of new data created in a single year is estimated to have increased to 35 zettabytes.

The notation immediately below the zetta is the exa (10^18). That notation is also of immediate importance because a 64-bit address space can “only” address up to 16 exabytes in existing architectures. Cisco estimates that global IP traffic in 2014 will reach 767 exabytes.

The significance of this much data is that the infrastructure necessary to create, transport, and store that much information has a growing impact on the data processing infrastructure—and particularly on the cost/performance ratio of memory technologies.

Most of us are familiar with the traditional computing memory hierarchy that describes the relative cost and performance of memory technologies as we move outward from high-performance cache memory at the closest physical and logical proximity to the processing element. As we move away from that position and toward the various levels of more remote data storage, the cost‑per‑bit and other performance requirements decline for memory technologies.

So what do we make of the recent introduction of lower-performance NAND replacing high-endurance and high-performance DRAM in a growing number of Enterprise SSD applications? And what about products such as Kaminario’s recently announced 12TB DRAM-based SSD?

The volume of data that is being processed, transported, and stored is beginning to shift the traditional cost/performance ratio of traditional semiconductor memory technologies. The lower power-consumption capabilities of NAND nonvolatile memory is already beginning to outweigh other performance considerations at this current level of 1.2 zettabytes of new data.

Our expectation is that this growth of data will continue to put pressure on system-level designers to find more opportunities for memory technologies to increase the value of their contribution to the overall system-level cost/performance. We believe that the opportunity for memory technologies to break away from the traditional image of the ultimate high-volume commodity product is rapidly approaching as new cost/performance opportunities are identified, and that system-level designers will continue to encourage new levels of technology experimentation and product differentiation among various memory technologies.

www.convergentsemiconductors.com - Global Analysis of Memory Strategies and Issues