Key words: Memory wall, Furber, ARM, Moore's Law, heterogeneous processing architecture
The observation by Intel co-founder Gordon Moore that the number of transistors on a circuit would double approximately every two years has been one of the most influential concepts in the growth of the semiconductor industry. An almost equally influential observation was the paper by William Wulf and Sally McKee in 1994 titled Hitting the Memory Wall: Implications of the Obvious, which posited that the rate of performance growth of memory technologies was not progressing as fast as was the performance growth of processors. This observation was labeled as the “memory wall,” and became axiomatic of the design concept by which the primary engine for OEM performance was the processor while the memory played a supporting role. In practical terms, this meant to the memory suppliers that the value of the memory products was essentially based on the cost per bit, and the basis for the competition among memory suppliers focused on the manufacturing efficiencies of a single memory product architecture. The primary focus of that competition was the constant reduction in the lithography in order to achieve more memory cells per silicon area.
We have now reached a level of manufacturing efficiency for memory products at which we are beginning to wonder how much further we can push stored charge memory technologies before the mass of the cells is too small to retain enough energy to be reliably used as an efficient information storage device.
Does this issue of continuing reductions in the storage mass of the memory cell represent yet another “memory wall” that further separates the value of memory technologies from the future development of logic devices?
Not necessarily. In fact, perhaps just the opposite effect is taking place.
You may recall Professor Furber, who designed the first ARM processor for Acorn Computers in the mid-80s. The successors to his design are currently enjoying broad success in high-volume mobile applications such as smart phones and tablet computers. Professor Furber recently stated that processors are also beginning to approach a limit at which the physics of the design cannot be supported. According to Professor Furber, the most advanced processors now contain transistors that are 100 to 150 atoms across, and the costs of designing controllable microchips are approaching a financial risk of a magnitude such that it alters the basic tenets of Moore’s Law.
"There are about 10 years to go before we reach the absolute limit. People have been saying that for 30 years, but this time I think it's probably right," he concludes.
Our point is that the technologies of today that are the basis for the high volume production of both logic circuitry and memory products are approaching similar technology hurdles. Regardless of when that hurdle is reached, that challenge will test both logic and memory technologies.
Professor Furber believes that the future architecture for processors will likely be parallel computing with problems split into separate discrete elements and solved simultaneously by different parallel of heterogeneous processing architectures.
We would also suggest that in addition to the shift toward multi-processing elements, the shift toward mobile devices that is already under way is an equally significant change in the market conditions. Shifting the target application for new memory technologies to a wider range of applications that includes mobile and lower power applications broadens the value proposition of the memory technologies beyond the single dominant high-volume commodity product. This new technology development track is distinctly different than memory technologies that extended the memory array architecture essentially from mainframe computers down to desktop PCs as the primary target application for the development of the next generation of high-volume memory technologies. However, this new technology development track for memory technologies is very much in line with the anticipated shift toward heterogeneous processing architectures with individualized memory performance requirements.
We believe that the development of new memory technologies in response to these anticipated hurdles is already far along the path toward commercialization; we may discover that the performance of the memory technologies is not the gating item to the system-level performance as we transition into the next phase of mobile and individualized processing applications.
www.convergentsemiconductors.com - Global Analysis of Memory Strategies and Issues
