Keywords: MCP, SiP, SOC, 3D IC, TSV, Moore’s Law, Multi-Chip Packaging
Why is the activity concerning multi-chip packaging (MCP) technologies increasing?
SEMATECH announced this week that ASE, Altera, Analog Devices, LSI, Qualcomm, and ON Semiconductor have all joined SEMATECH's 3D Enablement program. These companies will join CNSE, GlobalFoundries, Hewlett Packard, Hynix, IBM, Intel, Samsung, and UMC in a broad initiative—and to enable industry infrastructure for TSV-based 3D stacked IC solutions. Also in support of wafer and tool standards for TSV technology, SEMI has three task groups within its 3D IC group, with the formation of a fourth task group under way.
Global Semiconductor Association (GSA) also has a 3D/TSV Technology Working Group. At the recent GSA Memory Conference highlighting 3D Architecture with Logic and Memory Integrated Solutions, one speaker forecasted that stacked multiple wide I/O DRAMs would appear by 2015 using TSV, while another speaker predicted that the TSV-based wide I/O DRAM would not arrive until “…the second half of the decade.” Given the latitude in defining the marketing terms, these two statements aren’t really contradictory. I concluded that we are just a few product development cycles away from the commercial acceptance of TSV stacked memory die products (as early as 2014), to be followed by continuing high-volume expansion of this form factor.
This continuing interest in multi-die packages results from the shift away from Desktop PCs and toward mobile devices as the dominant target applications for new technologies. Product development emphasis continues to shift toward nonvolatile memory and smaller form factors supported by the further empowerment of single-core processors per by Moore’s Law.
Memory technologies immediately enter into the equation for mobile devices anywhere there is are processors. The architectural question is whether the memory requirement is small enough with enough process compatibility to be embedded in in large processor die (up to ~70% of the area in some cases) or System On Chip (SOC), or whether the memory requirement is large, complex enough, or requires enough flexibility in performance attributes to be better suited for a multi-die configuration in TSV or System-in Package (SiP).
That transition opens up the processing R&D and packaging possibilities for memory technologies, as is clearly shown by the ever-expanding number of part numbers and configurations supported by “DRAM companies.”
The broader implication is that the range of memory performance attributes continues to increase as the semiconductor industry identifies a widening set of new applications as targets for the development of new memory performance attributes. This trend implies a wider selection of memory interfaces, packaging options, performance attributes, and densities will continue to be developed. In particular, this leads toward a wider set of performance attributes that include not only the usual speed, density, power consumption, and cost/bit tradeoffs, but we also expect to see other variable performance tradeoffs to extend to cell endurance, latency, non-volatility, compatibility with logic processes, and time-to-market for new configurations.
We follow this trend closely and have several reports listed on our website detailing the strength and pervasiveness of this trend, and market opportunities it presents.
www.convergentsemiconductors.com - Global Analysis of Memory Strategies and Issues
