Learning Curves, SSOs, and Grand Strategies

Wikipedia defines “learning curve” as “a graphical representation of the changing rate of learning for a given activity or tool.” Learning curve theory is often referenced in the continuing efforts to reduce the average manufacturing cost of individual components, and the semiconductor utilization of the theory leads to an anticipation of decreasing manufacturing costs as a function of the number of units manufactured in a measured increment of time.

This concept is tied to another equally important, but often overlooked, role of Standards Setting Organizations (SSOs) to facilitate an infrastructure of support so that design activities can precede the actual availability of the next-generation product.  This insures that there is an established level of demand waiting as the new device ramps into production.

The combination of these two elements traditionally established a series of applications for new memory products, by which progressively higher volume applications transition to the next generation of memory product as the price per bit declined.  Although the highest volume application to convert was typically the desktop PC, that application tended to delay conversion to the newest and highest density product until the per bit cost was equivalent to the previous DRAM product generation.  This tends to be the common approach to increase the market share for any new product, and the decline in the price per bit of the memory technology is eventually a function of the total number of components manufactured and the fundamental manufacturability of the technology itself.  The concept leads to the careful selection of a market entry point and the identification of a series of applications with increasingly higher volume demand and increasingly lower cost targets. 

The previous blog ($300M Investment in Crocus’ TAS-MRAM) described a major investment by RUSNANO in support of TAS MRAM.  How does this measure up against the traditional approach described above?  Let’s revisit the practical marketing aspects of the learning curve theory.  Although the technical benefits of learning curve theory are well documented for established high-volume products, the theory is less effective as a tool for predicting the success of new technologies—particularly when those new technologies are being used to support new OEM applications. 

The recent TAS MRAM fab commitment by RUSNANO marks a different approach in which a grand strategy is envisioned that includes a substantial up-front investment rather than waiting for the growth in volume that traditionally resulted from the replacement of the previous generation of products with ones of roughly similar performance attributes.  The MRAM technology still has to demonstrate the manufacturing efficiencies and performance attributes to satisfy the needs of OEMs.  The distinction in this case, however, is that the initial growth in manufacturing and R/D knowledge will occur at a faster rate than can be obtained by relying only on learning curve benefits and the application-by-application replacement of an existing high-volume product.

The potential impact we see from the RUSNANO investment in TAS MRAM is that this high level of investment may also encourage enough support among potential OEMs to commit to the new technology at an earlier phase in the product development cycle.  As has been demonstrated by the increased usage of NAND to replace DRAM in some server architectures, the ability to influence the architecture of potential new OEM designs can be based on a broader set of criteria than the existing level of knowledge and specs.

It is this ability to potentially influence or stimulate new architectural designs that has now been introduced.  Data sheet comparisons of performance specs are always meaningful, but let’s not forget that the objective with new technologies is to influence the OEM’s future designs and new applications, and not necessarily to create a superior set of performance attributes for existing applications.  

We believe that the next phase of commercialization of new memory technologies has now begun.  OEMs have a basic understanding of the potential of the technologies as well as a perception of the fundamental shift in target applications for the new and emerging memory technologies, and the forward edge of competition is now shifting toward the manufacturing infrastructure.

www.convergentsemiconductors.com - Global Analysis of Memory Strategies and Issues 

$300M Investment in Crocus’ TAS-MRAM

Crocus has announced an investment of $300 million in the company and its Thermally Assisted Switching™ MRAM.  The investment comes from RUSNANO for creation of a manufacturing facility in Russia for medium- to high-density MRAM.  The two companies will form Crocus Nano Electronics (CNE) to build an advanced MRAM production facility in Russia capable of producing 90nm and 65nm material on Crocus’ TAS-MRAM technology.

Under the terms of the agreement, $125 million will be committed in the first year to set up the fab, and the existing investors of RUSNANO and Crocus will make an equity investment of $55 million into Crocus for additional technical development.  An additional $120 million will be scheduled for subsequent years for additional increases in the production capacity.  Further investments will be made at a later date in order to support future upgrades to 45nm processing.

The manufacturing flow will be designed to add MRAM-specific features within a standard 300mm CMOS process.   Initial operation is expected to begin within 2 years at 500 wafers per week, with the potential to double that capacity in a later phase of investment.  Crocus will also invest over $5 million initially into Russian research organizations in order to develop other advanced manufacturing solutions as part of the support infrastructure.

This manufacturing strategy compliments Crocus’ existing 130nm foundry partnership with TowerJazz, which is currently in the final qualification stages with production planned by the end of this year.  Processing contributions of San Jose’s Silicon Valley Technology Center (SVTC) also should be acknowledged.

Crocus’ investor RUSNANO was established through the reorganization of the corporation formerly known as the Russian Corporation of Nanotechnologies.   Anatoly Chubais is now serving as chairman of the Executive Board. In Autumn 2009, the supervisory council of RUSNANO approved the corporation’s participation in a new Russian venture fund established in partnership with VTB Group and well-known Silicon Valley investment company Draper Fisher Jurvetson to focus on promising nanotechnology innovation.  RUSNANO has since committed $5.9 billion to 110 projects with more than $2.4 billion already invested, and has opened an office on Sand Hill Road in San Jose.

One of the competitive elements we advise clients engaged in new memory technologies to heed in their business development practices is to avoid becoming too focused on the item-by-item comparison of their data sheets with those of their potential competitors.  Participation in emerging markets and with emerging technologies often includes another important element, which is the ability of a competitor to exert an influence on the architecture of future products beyond just the performance attributes of the data sheets.  We place this announcement by Crocus in that category of potentially game-altering events.  The commitment to a significant volume of manufacturing capacity by CNE and the presence of an influential new supporter in RUSNANO has to be acknowledged as substantially raising the ante in the development of new memory technologies.

www.convergentsemiconductors.com - Global Analysis of Memory Strategies and Issues 

Panasonic ReRAM Samples Scheduled for Late 2011

Panasonic issued a brief announcement today that the company anticipates availability of 2 megabit ReRAM samples by the end of this year, with expectations of mass production in 2012. The company intends to focus on small-capacity non-volatile ReRAM configurations intended for home electronic products.

ReRAM tends to cover a wide range of materials, and it is not clear from today’s brief announcement what material was used in the process.

However the announcement follows a paper presented at the International Electron Devices Meeting (IEDM) in San Francisco in December 2008. That paper described a tantalum and oxygen (TaOx) process for a non-volatile memory cell with endurance over 109 cycles and data retention in excess of 10 years at 85 degrees centigrade. At that time, the company had produced 8 Kbit 1T1R memory arrays using a standard 0.18 micron CMOS process.

Key words: ReRAM Panasonic Tantalum TaOx

www.convergentsemiconductors.com - Global Analysis of Memory Strategies and Issues 

FRAM Perspective

2011 has been a hectic year so far for FRAM programs.

After achieving total revenue of $47.5 million for 2009, followed by total revenue of $70.2 million 2010, the first quarter of this year brought organizational changes to Ramtron as well as announcements of delays in IBM’s planned FRAM-foundry program. IBM’s program for a 0.18-micron process began in 2009 with the intention of joining TI and Fujitsu with FRAM foundry services for Ramtron, and production material was intended for 2010.

However the outlook for the technology has improved significantly in May with a major announcement from Texas Instruments. Based on material from the company’s 130-nm technology process, TI has announced the industry's first ultra-low-power FRAM 16-bit microcontrollers with the capability to write more than 100 times faster than Flash and EEPROM-based microcontrollers, while using as little as 250 times less power. Additionally, the on-chip FRAM memory allows data retention in all power modes, supports more than 100 trillion write cycles, and delivers a new dimension of flexibility by allowing developers to partition data and programming memory with changes in software. The FR57xx series eliminates existing power consumption and write endurance barriers, enabling more cost-efficient data logging, remote sensing and wireless update capabilities. The design also enables intelligent battery-less RF connectivity solutions, which have been the hallmark of FRAM’s low power characteristics. Ramtron’s MaxArias series of products also takes advantage of energy harvesting from RF energy. For more information on TI's new FR57xx microcontrollers with proven FRAM memory, follow this link.

TI maintains that its proprietary process technology, jointly developed with FRAM partner Ramtron, enables it to integrate its MCU with an FRAM option along with other analog options onto the same chip. The essence of TI’s new microcontroller lies in its “ultra-low power embedded memory,” according to Scott Roller, vice president of microcontroller products at TI, in an interview with EE Times. “If you can drive down the power consumption, new markets will be created. That’s been always our fundamental belief at TI.” 

TI isn’t the only company to embed FRAM into microcontrollers. Fujitsu introduced a single-chip, 8-bit MCU featuring embedded FRAM in late 2010 which is intended for a variety of general-purpose applications, including consumer electronics products, healthcare and industrial systems. 

We believe that this is once again demonstrates the growing acceptance of product differentiation based on a wider range of memory performance attributes, and we expect that the performance capabilities of MCUs will continue to be an important opportunity for new memory technologies. 

Key words: FRAM, ferro-electric, Texas Instruments, TI, Ramtron, IBM, Fujitsu, MCU, memory technology

www.convergentsemiconductors.com - Global Analysis of Memory Strategies and Issues 

Lithium-ion Battery —Supply Issues Ahead?

Key words: Lithium-ion, battery, li-ion, shortages

The impact of the catastrophic earthquake and subsequent events in Japan are not yet (and may never be) fully understood, EXCEPT that those events have had and will continue to have a real effect on all manufacturers and consumers of lithium-ion power cells. The question for the next few months or so may turn out to be—Got batteries?

The expected 42% annual increase in demand for tablets, eReaders and Smartphones in 2011 has battery vendors looking ahead to substantially increased demand; all other mobile products are forecast to have double-digit demand growth as well. Convergent Semiconductors forecasts that the first impact to lithium-ion battery supply will be felt this May and June.

The Eastern Japan earthquake, tsunami and nuclear power plant news about wafers, semiconductor supply and the impact on automakers has been in the news. What has not been in the news is the effect on the five Japanese chemical companies that supply nearly all materials to the world’s battery manufacturers. Even as the chemical companies recover and repair the direct damage to their plants, the question of the infrastructure problems needs to be resolved. The evacuation zone around the Fukushima Nuclear Power Plant and rolling blackouts are issues that must be taken into account.

All of the top battery companies, Panasonic-Sanyo, Sony, Samsung SDI, and LGC, depend upon chemical suppliers with manufacturing located in the Eastern Japan region. There are seven chemical companies that were damaged by the earthquake/tsunami/power plant disaster. These companies are not all the major suppliers of specific chemicals, but are part of a supply chain that works with an ever-increasing battery demand.

While the Korean battery manufacturers have taken over market share leadership for lithium-ion batteries consumed by PCs and other mobile products, the Japanese material suppliers have remained dominant in the key chemical components for batteries no matter where those batteries are manufactured. May and June will start to exhibit supply interruptions for mobile products ranging from notebooks and tablets to power tools. Expect to see push-outs of new product announcements until a secure battery supply has been established. Meanwhile, tough competitors are using creative cooperation to ensure the user is not forced into some other technology.

For example, Sony committed to produce certain lithium batteries in March and April but could not deliver due to the quake. Panasonic, at Sony’s request, took over production and adjusted the number and types of batteries in order to deliver a workable solution.

Makita purchased lithium-ion batteries for power tools from Sony but now appears to have gone to Samsung SDI for its supply of lithium-ion batteries. According to an insider, Makita placed an exceptionally large battery order in expectation of strong reconstruction demand in the wake of the earthquake.

Lithium-ion batteries are usually available everywhere. They are the ubiquitous item on the bill of materials that OEMs take for granted will always be available…whenever. Then there is a catastrophic earthquake/tsunami/nuclear power plant failure in Japan—home of single source chemicals for the global battery industry. Hence the essential drama of our battery report—which of your high volume, high dollar consumer electronics products depends on a one-dollar li-ion battery formerly manufactured in the Evacuation Zone?

Convergent Semiconductors covers this market to provide a strategic view of the mobile products phenomenon. Expect delays in product introductions and push-outs in delivery because of the broken supply chain of deliveries from chemical companies in Japan to its global customers. The industry will solve this problem. New sources in a variety of locations will be established. The companies in Japan will recover. However, in the near future, batteries will be a limiting component on the BOM. Contact us for more details of report.

www.convergentsemiconductors.com - Global Analysis of Memory Strategies and Issues 

Is the Semiconductor “Memory Wall” Finally Crumbling?

Key words: Memory wall, Furber, ARM, Moore's Law, heterogeneous processing architecture

The observation by Intel co-founder Gordon Moore that the number of transistors on a circuit would double approximately every two years has been one of the most influential concepts in the growth of the semiconductor industry. An almost equally influential observation was the paper by William Wulf and Sally McKee in 1994 titled Hitting the Memory Wall: Implications of the Obvious, which posited that the rate of performance growth of memory technologies was not progressing as fast as was the performance growth of processors. This observation was labeled as the “memory wall,” and became axiomatic of the design concept by which the primary engine for OEM performance was the processor while the memory played a supporting role. In practical terms, this meant to the memory suppliers that the value of the memory products was essentially based on the cost per bit, and the basis for the competition among memory suppliers focused on the manufacturing efficiencies of a single memory product architecture. The primary focus of that competition was the constant reduction in the lithography in order to achieve more memory cells per silicon area.

We have now reached a level of manufacturing efficiency for memory products at which we are beginning to wonder how much further we can push stored charge memory technologies before the mass of the cells is too small to retain enough energy to be reliably used as an efficient information storage device.

Does this issue of continuing reductions in the storage mass of the memory cell represent yet another “memory wall” that further separates the value of memory technologies from the future development of logic devices?

Not necessarily. In fact, perhaps just the opposite effect is taking place.

You may recall Professor Furber, who designed the first ARM processor for Acorn Computers in the mid-80s. The successors to his design are currently enjoying broad success in high-volume mobile applications such as smart phones and tablet computers. Professor Furber recently stated that processors are also beginning to approach a limit at which the physics of the design cannot be supported. According to Professor Furber, the most advanced processors now contain transistors that are 100 to 150 atoms across, and the costs of designing controllable microchips are approaching a financial risk of a magnitude such that it alters the basic tenets of Moore’s Law.

"There are about 10 years to go before we reach the absolute limit. People have been saying that for 30 years, but this time I think it's probably right," he concludes.

Our point is that the technologies of today that are the basis for the high volume production of both logic circuitry and memory products are approaching similar technology hurdles. Regardless of when that hurdle is reached, that challenge will test both logic and memory technologies.

Professor Furber believes that the future architecture for processors will likely be parallel computing with problems split into separate discrete elements and solved simultaneously by different parallel of heterogeneous processing architectures.

We would also suggest that in addition to the shift toward multi-processing elements, the shift toward mobile devices that is already under way is an equally significant change in the market conditions. Shifting the target application for new memory technologies to a wider range of applications that includes mobile and lower power applications broadens the value proposition of the memory technologies beyond the single dominant high-volume commodity product. This new technology development track is distinctly different than memory technologies that extended the memory array architecture essentially from mainframe computers down to desktop PCs as the primary target application for the development of the next generation of high-volume memory technologies. However, this new technology development track for memory technologies is very much in line with the anticipated shift toward heterogeneous processing architectures with individualized memory performance requirements.

We believe that the development of new memory technologies in response to these anticipated hurdles is already far along the path toward commercialization; we may discover that the performance of the memory technologies is not the gating item to the system-level performance as we transition into the next phase of mobile and individualized processing applications.

www.convergentsemiconductors.com - Global Analysis of Memory Strategies and Issues