Solid State Disk (SSD) demand is pushing in two directions; SSD and USB flash drives for mobile consumer applications, as well as higher-performance SSDs for server-level performance improvements in data retrieval. Both market trends are well established and easily differentiated.
There are, however, several technical barriers ahead for NAND endurance related to block erase/write cycles as cell sizes shrink and as page sizes increase. The endurance of the cells is reduced in both cases, but the application impact and response is not the same for both the consumer and enterprise applications.
Mobile consumer applications are cost/density driven and the potential solutions are more easily addressed due to the shorter product life expectancy.
The duty cycle life expectancy of the higher performance enterprise applications is more challenging. Providing hot-swap capabilities for NAND boards as they approach the end of their reliability limits is a well-proven method to assure the reliability of the data, and the additional cost of substituting new boards as older boards approach the end of their useful life is easily justified relative to the increase in performance.
However we are likely to eventually experience a fundamental shift in the historic progression of the memory cost/performance equation as smaller geometry manufacturing processes of today's technologies inevitably begin to reduce the endurance characteristics of erase/re-write cycles.
Deviations from the traditional decline in the cost-per-bit due to increasing manufacturing challenges at sub-20nm processes, as well as any additional architectural and error-correction requirements necessary to assure the reliability of the data, will slow the rate of decline in the bit cost of the memory technology and provide market entry points for newer semiconductor memory technologies.
This is an important element in the product development path that leads to the introduction of new memory technologies with their plethora of new high-performance attributes. The assumption that existing memory technologies-particularly NAND-can continue the traditional annual decline in the cost-per-bit indefinitely without a reduction in the performance characteristics is no longer considered valid.
There are, however, several technical barriers ahead for NAND endurance related to block erase/write cycles as cell sizes shrink and as page sizes increase. The endurance of the cells is reduced in both cases, but the application impact and response is not the same for both the consumer and enterprise applications.
Mobile consumer applications are cost/density driven and the potential solutions are more easily addressed due to the shorter product life expectancy.
The duty cycle life expectancy of the higher performance enterprise applications is more challenging. Providing hot-swap capabilities for NAND boards as they approach the end of their reliability limits is a well-proven method to assure the reliability of the data, and the additional cost of substituting new boards as older boards approach the end of their useful life is easily justified relative to the increase in performance.
However we are likely to eventually experience a fundamental shift in the historic progression of the memory cost/performance equation as smaller geometry manufacturing processes of today's technologies inevitably begin to reduce the endurance characteristics of erase/re-write cycles.
Deviations from the traditional decline in the cost-per-bit due to increasing manufacturing challenges at sub-20nm processes, as well as any additional architectural and error-correction requirements necessary to assure the reliability of the data, will slow the rate of decline in the bit cost of the memory technology and provide market entry points for newer semiconductor memory technologies.
This is an important element in the product development path that leads to the introduction of new memory technologies with their plethora of new high-performance attributes. The assumption that existing memory technologies-particularly NAND-can continue the traditional annual decline in the cost-per-bit indefinitely without a reduction in the performance characteristics is no longer considered valid.
